We are a design services firm specializing in cutting-edge semiconductor solutions. With a relentless commitment to innovation and a passion for pushing the boundaries of technology, we have established ourselves as a trusted partner for companies seeking top-tier semiconductor design and development expertise.


GMS specializes in Custom Analog, Digital & Mixed Signal design.
With deep roots in Memory Design (DRAM, SRAM, Emerging NVM) and by extension in Compute-In-Memory architectures,
GMS is a one-stop-shop for implementing complex functionalities and algorithms into proven silicon.

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GMS typically works in highly demanding and challenging markets targeting optimized Small Weight and Power (SWaP) performances.

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GMS is active in the community through the publication of core white papers, on its own or in partnership with its systems-level clients.

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Our story started as the project of three friends and colleagues. It evolved into a highly professional design organization, staffed by a large crew of sound experts, and constituting a strong workforce to tackle challenging use cases.

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News Room

Stay connected with us through exploring our blog that features the latest news in our world.

Green Mountain is hiring a Circuit Design Engineer

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Green Mountain Semiconductor spikes for NASA

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Green Mountain awarded a NASA Phase II contract

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Memcon 2024

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GOMACTech 2024

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LPDDR4/4X/5 secondary PHY available

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Custom ASIC Design Services

GMS specializes in Custom Analog, Digital & Mixed Signal design . GMS engineers have deep ties to Memory Design (DRAM, SRAM, Emerging NVM) and collectively taped-out a high number of DRAM circuits. 

This unique capability is combined with a know-how in logic design, both for high speed interfaces but also for general purpose full custom ASIC development.

AI Circuit Design

GMS has a long history in memory design and has been working with In-memory computing since 2015.

In-Memory Computing

Green Mountain Semiconductor has a long history in memory design, both from within the company itself and from prior work experience of our team.

Previous Experience

GMS has been doing fundamental research on compute-in-memory architectures since 2016 and filed 7 patents so far on this topic. GMS is focusing on ultra-low power in-memory neural networks for autonomous AI inferencing. This led to several development contracts with NSF and more recently with NASA. GMS is currently sponsored by this agency for designing a family of rad-hard neuromorphic processors.

Patented Technology

Green Mountain Semiconductor has several patents granted and pending in the field of commodity memory architecture, error correction code and in-memory high-parallel data processing.

Analog & Mixed Signal Design

While we also use state of the art digital tool flows where appropriate, the real world is still analog.

Analog Design

While we also use state of the art digital tool flows where appropriate, the real world is still analog. Some of our products need carefully regulated internal voltages and charge pumps along with sophisticated level shifters, others need programmable H-bridge current drivers and low-noise differential amplifiers.

Full Custom Development

Our R&D team is experienced in designing ASICs from the early technology development up to the test chips and associated test programs for functionality / yield assessment & monitoring.

Special Purpose Applications

We develop advanced concepts, IP & Asics for special applications that cannot reuse commercial off the shelf solutions.

Special Purpose Applications

Green Mountain Semiconductor is 100% US based. All of our designs are performed by our own employees at our offices in Burlington, VT.

Interface Solutions

GMS has the experience to develop high specific speed PHY interfaces based on its expertise around memories. It developed a family of secondary LPDDR4/4X/5 PHY as well as SPI/QPI.

High speed PHY’s

GMS has the experience to design high speed interfaces for general purpose data transfer, while adhering to the well known and well defined standards, for instance the ones specified by JEDEC. GMS has a track record in advanced technology nodes such as
7nm TSMC.


Green Mountain Semiconductor Inc. excels in offering advanced semiconductor solutions to a diverse array of industries. Our extensive expertise allows us to contribute meaningfully to sectors where precision and innovation are paramount. Whether addressing the complex needs of cutting-edge aerospace systems, advancing medical technology, or powering high-speed computing platforms, our commitment to excellence and innovation extends across various key markets.

White Papers

Our firm has authored a multitude of comprehensive white papers. We invite you to explore our library. For full access and the ability to download any of our papers, please submit a request for access.

Co-design of a novel CMOS highly parallel, low-power, multi-chip neural network accelerator

Why do security cameras, sensors, and Siri use cloud servers instead of on-board computation? The lack of very low power, high-performance chips greatly limits the ability to field untethered edge devices. We present the NV-1, a new low-power ASIC AI processor that greatly accelerates parallel processing (10X) with dramatic reduction in energy consumption (>100X), via many parallel combined processor-memory units, i.e., a drastically non-von-Neumann architecture, allowing very large numbers of independent processing streams without bottlenecks due to typical monolithic memory. The current initial prototype fab arises from a successful co-development effort between algorithm- and software-driven architectural design and VLSI design realities. An innovative communication protocol minimizes power usage, and data transport costs among nodes were vastly reduced by eliminating the address bus, through local target address matching. Throughout the development process, the software/architecture team was able to innovate alongside the circuit design team’s implementation effort. A digital twin of the proposed hardware was developed early on to ensure that the technical implementation met the architectural specifications and, indeed, the predicted performance metrics have now been thoroughly verified in real hardware test data. The resulting device is currently being used in a fielded edge sensor application. Additional proofs of principle are in progress, demonstrating the proof on the ground of this new real-world extremely low-power high-performance ASIC device.

May 15, 2024

Opportunities and Limitations of in-Memory Multiply-and-Accumulate Arrays

In-memory computing is a promising solution to solve the memory bottleneck problem which becomes increasingly unfavorable in modern machine learning systems. In this paper, we introduce an architecture of random access memory (RAM) incorporating deep learning inference abilities. Due to the digital nature of this design, the architecture can be applied to a variety of commercially available volatile and non-volatile memory technologies. We also introduce a multi-chip architecture to accommodate for varying network sizes and to maximize parallel computing ability. Moreover, we discuss the opportunities and limitations of in-memory computing as future neural networks scale, in terms of power, latency and performance. To do so, we applied this architecture to various prevalent neural networks, e.g. Artificial Neural Network (ANN), Convolutional Neural Network (CNN) and Transformer Network and compared the results.

January 01, 2021

Design and Testing Considerations of an In-Memory AI Chip

In-memory computing is a propitious solution for overcoming the memory bottleneck for future computer systems. In this work, we present the testing and validation considerations for a programmable artificial neural network (ANN) integrated within a phase change memory (PCM) chip, featuring a Nor- Flash compatible serial peripheral interface (SPI). In this paper, we introduce our method for validating the circuit components specific to the ANN application. In addition, high-density in- memory multi-layer ANNs cannot be manufactured without testing and repair of the memory array itself. Therefore, design for testability (DFT) features commonly used in commodity or embedded memory products must be maintained as well. The combination of these two test/characterization steps alleviates the need to test the actual inference functionality in hardware.

January 01, 2020

Ecosystem Partners

GMS works with key stakeholders in the industry, from research institutions to core manufacturing and assembly partners. A few of these partners are mentioned below.

Aragio SolutionsIP ProviderWebsite
ArmIP ProviderWebsite
Global FoundriesFoundryWebsite
QP TechnologiesPackaging & Test HouseWebsite
SkyWater TechnologyFoundryWebsite
SUNY AlbanyAcademiaWebsite