Lorem ipsum dolor sit amet, consectetur adipiscing elit. Ut eu ex nec lorem fringilla lacinia. Vivamus mollis lectus sed erat tincidunt, at cras amet.
GMS has the experience to develop high specific speed PHY interfaces based on its expertise around memories. It developed a family of secondary LPDDR4/4X/5 PHY as well as SPI/QPI.
GMS has the experience to design high speed interfaces for general purpose data transfer, while adhering to the well known and well defined standards, for instance the ones specified by JEDEC. GMS has a track record in advanced technology nodes such as
7nm TSMC.
Our firm has authored a multitude of comprehensive white papers. We invite you to explore our library. For full access and the ability to download any of our papers, please submit a request for access.
In addition to our custom design service, Green Mountain Semiconductor has ownership of multiple IP's and is available for IP development services.
This LPDDR4/4X/5 PHY is a memory-side interface IP normally found
implemented within commodity DRAM products. Green Mountain
Semiconductor's LPDDR4X/LPDDR5 combo IP provides the unique opportunity
to transmit data between a variety of devices such as AI coprocessors,
in-memory compute solutions and emerging memory products.
This is a memory side (Slave-side) interface for AI processors and
other ASICS seeking the latest high speed, low power LPDDR interface
protocols for general purpose data transfer, while adhering to the well
known and well defined LPDDR4X and LPDDR5 standard as specified by
JEDEC.
This IP is designed for 7nm TSMC but can be ported to other logic
processes. It is also suitable for a wide variety of memories such as
DRAM, SRAM as well as emerging memories including non-volatile memories,
with appropriate modifications.
This LPDDR4X PHY is a memory-side interface IP normally found
implemented within commodity DRAM products. Green Mountain
Semiconductor's LPDDR4X IP provides the unique opportunity to transmit
data between a variety of devices such as AI coprocessors, in-memory
compute solutions and emerging memory products.
This is a memory side (Slave-side) interface for AI processors and
other ASICS seeking the latest high speed, low power LPDDR interface
protocols for general purpose data transfer, while adhering to the well
known and well defined LPDDR4X standard as specified by JEDEC.
This IP is designed for 7nm TSMC but can be ported to other logic
processes. It is also suitable for a wide variety of memories such as
DRAM, SRAM as well as emerging memories including non-volatile memories,
with appropriate modifications.
This LPDDR5 PHY is a memory-side interface IP normally found implemented
within commodity DRAM products. Green Mountain Semiconductor's LPDDR5
IP provides the unique opportunity to transmit data between a variety of
devices such as AI coprocessors, in-memory compute solutions and
emerging memory products.
This is a memory side (Slave-side) interface for AI processors and
other ASICS seeking the latest high speed, low power LPDDR interface
protocols for general purpose data transfer, while adhering to the well
known and well defined LPDDR5 standard as specified by JEDEC.
This IP is designed for 7nm TSMC but can be ported to other logic
processes. It is also suitable for a wide variety of memories such as
DRAM, SRAM as well as emerging memories including non-volatile memories,
with appropriate modifications.
This LPDDR5X PHY is a memory-side interface IP normally found
implemented within commodity DRAM products. Green Mountain
Semiconductor's LPDDR5X IP provides the unique opportunity to transmit
data between a variety of devices such as AI coprocessors, in-memory
compute solutions and emerging memory products.
This is a memory side (Slave-side) interface for AI processors and
other ASICS seeking the latest high speed, low power LPDDR interface
protocols for general purpose data transfer, while adhering to the well
known and well defined LPDDR5X standard as specified by JEDEC.
This IP is designed for 7nm TSMC but can be ported to other logic
processes. It is also suitable for a wide variety of memories such as
DRAM, SRAM as well as emerging memories including non-volatile memories,
with appropriate modifications.
This SPI/QPI PHY IP is fully compatible with Macronix NOR Flash SPI products. Max frequency hardware proven is 133MHz.Can be used for a variety of memory products and in-memory AI embedded systems.
Test bench is included.
Deliverables
Hard IP or Soft IP on request
Custom modification, porting to your desired technology and verification available on request. We are a full features turn-key design house able to port this IP to any suitable target technology.
This SPI Slave interface is easily ported to other CMOS technology nodes with available standard cell and GPIO library.
